Flip-chip semiconductor devices, such as those using Controlled Collapse Chip Connection (C4) or other bump technologies, have the advantage of establishing a high input/output (I/O) count. A large number of I/Os can be formed on a flip-chip device because traditional peripheral spacing limitations of wire bonded and TAB (tape automated bonding) devices are eliminated. Not only can the number of I/Os increase on a flip-chip device, but the actual space that the device takes up on a user substrate is reduced since conventional packaging elements and materials are not necessary. A further advantage which semiconductor manufacturers have realized is that a C4 or other bump configuration can be established on a product without significant changes to existing semiconductor die designs for flip-chip applications. For example, an existing product which is available in a wire bonded or a TAB bonded configuration can be transformed into a C4 configuration with only back-end manufacturing changes, specifically with the addition of a redistribution metallization process. Die fabrication up to the point of forming bond pads on the semiconductor die is identical between products which will be offered in a C4 configuration and those that will be offered in a wire bonded or TAB bonded configuration. After bond pads are formed, wire bonded and TAB bonded devices proceed to final passivation, while C4 devices undergo the redistribution metallization process. The redistribution metallization process involves depositing an additional metal layer, patterning that metal layer to form interconnects which connect the bond pads to patterned C4 bump pads. In other words, the redistribution metallization layer is used to redistribute the peripheral bond pad configuration into a C4 array or partial array pad configuration. After the redistribution metallization is patterned, final passivation is deposited, and etched to leave access to the C4 bump pads. A barrier metal or series of metals may then be deposited onto the C4 bump pads through a shadow mask. After any barrier metal is deposited, solder is deposited through the same mask to form solder bumps on each of the C4 pads.
While the ability to use the same die design in both C4 configurations and wire bonded or TAB bonded configurations is advantageous from a die manufacturing point of view, there are disadvantages associated with the ability to probe the bumped semiconductor die. After die fabrication is complete, semiconductor wafers are probed to test the functionality of the individual die on the wafer. In wire bonded and TAB bonded devices wherein bond pads are peripherally located around the semiconductor die perimeter, probing is accomplished using a probe card having cantilever probe needles arranged to match the bond pad configuration. With flip-chip or C4 devices where there are solder bonds formed on the pads which are in an array configuration or partial array configuration, there are several problems associated with the wafer probing operation. One problem is that bond pads may not be available for contacting with the probe needle. For instance, a C4 bump may be formed directly or partially over a bond pad so that in order to probe that particular pad the cantilever needle must probe the actual C4 bump. This may lead to mechanical damage of the C4 bump, thereby degrading the integrity of the device as a whole. Another problem in using cantilever probes in conjunction with flip-chip or C4 devices is that the C4 bumps are typically not arranged in a peripheral configuration. Rather, the C4 bumps are arranged in an array configuration where individual C4 bumps may be located several rows deep from the perimeter of the die. In such instances, it is very difficult and sometimes impossible to maneuver cantilever probe needles to such internal C4 bumps without interfering with other probe needles.
A known procedure for probing C4 devices which is simple and inexpensive is to form the C4 bumps and redistribution metal layer such that the peripheral bond pads remain accessible to probe needles. However, this solution is limited to instances where no C4 bumps are formed directly over bond pads. C4 bumps are often formed directly over bumps to minimize interconnect distance, thereby improving device performance or to provide more area on the die to place the bumps.
Another solution to the aforementioned problems associated with probing bumped semiconductor wafers is the use of an array probe. In place of a probe card using cantilever probe needles, an array probe utilizes a probe card having a space transformer. The array probe is used as a replacement to the cantilever probe needles and consists of a plurality of conductive wires or conductive bumps which are electrically connected to a probe card. A significant disadvantage of array probes, however, is that these probes are extremely expensive, and the lead time for developing an array probe for a new product is extremely long.